Experienced Soc/ip/mcu Design Verification Engineer (from 1 Year Experience)

Greetings from Renesas!
We are the world No.1 supplier of MCU/SoC, providing cutting edge solutions for global automotive customers:
1/ Autonomous driving car
2/ Autosar
3/ Safe driving/ steering/ braking systems
4/ Car infotainment & ADAS (Advanced Driver Assistance Systems)
Now, we are seeking talented engineers for our automotive projects at Renesas Vietnam (District 7, HCMC)!
1. System-on-chip (SoC) for Car Infotainment, ADAS application
a. Designing, Integrating whole system including processor, bus, peripheral
b. Verification at both module and system level
2. Microcontroller (MCU) for Automotive (Engine control, Chassis control…)
a. Designing, Integrating whole system including microcontroller, peripheral
b. Verification at both module and system level
3. IP including Processor and Designing platform for SoC, MCU development
a. Integrating of ARM® related Processor Core
b. Designing of Renesas in-house Processor Core
c. Designing of keys Multimedia IP (Video Signal Processor, Video Encoder/Decorder)
d. Designing of Simulation Platform for accelerating SoC/MCU development, early software development, error simulation, performance evaluation.
4. Ambassador IP Development for AMBA bus system
a. Developing the bus bridge and interconnect library IP for AMBA BUS system generation tool. The development includes IP design and IP Verification (full flow or partial).
b. Making Functional Specification, Detail Logic Design Specification, RTL coding and Verification.
c. Building Random environment with SV-UVM (and Formal Verification as planned) using the latest EDA tool from Cadence & Synnosys (e.g IWB, vManager, SimVision, and JasperGold, VCS, Verdi,...)
d. Analyzing logic structure and feedback for improvement.
5. Hardware CodecIP Development (AV1, HEVC, JPEG, …)
a. Developing Hardware Codec IPs for 2022 products. The scope (related tools/languages) of design:
b. Making detail specification from requirement (HWM, basic spec)
c. Designing C++/SystemC/Verilog based on detail specification
d. Checking error of C++/SystemC/Verilog (C/C++, Verilog, ...)
e. Verifying plan to ensure no bug after release (office tools,...) and the design on HW Manual
f. Making test bench, patterns, scripts for verification task ( C/C++, Verilog, perl, csh, ...)
g. Perform verification (UT, CT) as plan, report and fix all defects (Visual C, GCC, VCS, ...)
h. Logic design (logic synthesis, gate netlist checkers, DFT, STA) (Design Compiler, …)

- At least 1-year experience in logic design and verification of SoC, MCU, IP, CPU
- Hardware verification languages (Verilog, System Verilog), System Verilog Assertion (SVA), Verification methodology (UVM, VMM)
- Scripting languages (PERL, shell, etc.)
- Solid knowledge of EDA tool (ex: VCS/NC, Design-Compiler, Formality/Conformal)
- Functional Safety Experience (ISO 26262) is a strong plus
- Good at English communication