Physical Design Engineer

APR / Physical Implementation

Solve congestion issues and balance PPA (performance, power, area).
Perform partitioning, placement optimization, CTS, routing, and post- route optimization.
Take customer netlists and execute the complete physical design flow from floorplanning to chip finishing (GDSII).

STA / Timing Closure

Run static timing analysis (STA) across multi- corner and multi- mode scenarios.
Perform timing ECOs and work closely with RTL/logic teams.
Debug and fix setup, hold, and DRVs.

Physical Verification (PV)

Handle density, antenna, and manufacturability checks.
Ensure layout- to- netlist consistency.
Run and debug DRC, LVS, LVL, PERC, ERC checks.

Power / IR Drop / EM Analysis

Identify weak PDN areas, voltage drops, and high resistance paths.
Perform IR drop and EM analysis.
Propose improvements to PDN and optimize power.

Automation & Customer Support

Contribute to methodology development and tool evaluation.
Develop automation scripts (TCL, Perl, Shell, or Python).
Provide technical support and communication with customers and internal teams.

Project Quality & Collaboration

Follow best practices and sign- off checklists.
Track progress, identify risks, and report status.
Mentor junior engineers when needed.

Nice- to- have: Advanced technology node experience (28nm, 16nm, FinFET), tape- out experience, low- power design, and leadership skills.
Experience in IR/EM analysis and fixing power integrity issues.
Strong STA, timing ECO, and sign- off closure skills.
Strong scripting (TCL, Perl, Shell, Python).
Bachelor’s or higher degree in EE/Telecom/VLSI/Microelectronics.
Good English communication skills.
Proficient in ICC2, Innovus, PrimeTime, RedHawk/Voltus, Calibre.
Minimum 3 years’ hands- on experience in physical design (Netlist → GDSII).

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Cập nhật gần nhất lúc: 2025-11-29 19:40:03