Design Verification Engineers

Testbench development/modification
To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations.
Regressions, coverage analysis
Verification closure
To ensure process compliance in the assigned module| and participate in technical discussions/review.
Full chip test plan development/modification
Test case development, coding, execution, bug analysis

Experience with Gate level simulations.
Experience with Testbench development/modification, Test case development, coding, execution, bug analysis, Regressions, coverage analysis, Verification closure.
Should have participated in multiple ASIC/SoC verification till tape out stage.
Experience with Full chip test plan development/modification.
Bachelors/Master’s degree in Electronics /Electrical Engineering with 5+ years’ experience in verification.
Experience in scripting.
Be able to use English in working communication (read and write)
Good understanding of ASIC/SoC life cycle.

100% salary during probation time 
100% of full salary and benefits as an official employee from the 1st day of working 
Working in a fast paced, flexible, and multinational working environment with opportunity to travel onsite (in 49 countries) 
Attractive package including base salary + 13th month salary + Performance Bonus.  
Insurance based on full base salary and Medical Benefit (Bao Viet Insurance Package) for Employee and Family 
Internal Training (Technical & Functional & English) 
Working with outstanding colleagues coming from top universities and top companies in Vietnam and foreign countries

Cập nhật gần nhất lúc: 2024-04-03 11:42:21