Senior Design Verification Engineers (Hybrid)

Develop and implement verification plans to ensure the functional correctness of VLSI designs before they are fabricated.
Enhance existing verification tools and processes to improve efficiency and effectiveness of the verification workflow.
Create and maintain verification environments using advanced verification methodologies such as UVM (Universal Verification Methodology), OVM (Open Verification Methodology), or VMM (Verification Methodology Manual).
Write and debug test cases, manage regression test suites, and analyze coverage reports to ensure comprehensive testing of VLSI designs.
Stay updated with the latest trends and developments in VLSI verification methodologies and technologies.
Mentor junior verification engineers and lead verification teams to achieve project goals within designated timelines.
Collaborate with design engineers to identify and resolve design issues detected during the verification process.

Essential Skills

Strong debugging skills and familiarity with simulation tools such as Cadence Xcelium, Mentor Questa, or Synopsys VCS.
Expertise in SystemVerilog and any of the major verification methodologies like UVM, OVM, or VMM.
In- depth knowledge of digital circuit design and verification.
Ability to develop verification plans that align with project scope and design complexity.

Desirable Skills

Leadership skills with experience managing small teams or leading verification projects.
Familiarity with advanced verification features such as assertions and functional coverage.
Knowledge of ASIC or FPGA design flow.
Experience with formal verification tools and methodologies.

Experience with scripting languages such as Python, Perl, or Tcl is highly desirable.
Strong analytical and problem- solving skills, with a proven track record of finding and fixing design flaws.
Excellent communication skills, both verbal and written, with the ability to work effectively in a team environment.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Proficient in SystemVerilog and at least one verification methodology (UVM, OVM, VMM).
Minimum of 5 years of experience in VLSI design verification.

Flexibility in work hours and the possibility of remote work arrangements, depending on project requirements.
Supportive work environment that encourages innovation and continuous learning.
Competitive salary and benefits package including bonuses, health insurance, and retirement plans.
Opportunities for professional growth and advancement within the company.
Access to the latest tools and technologies in the field of VLSI design verification.

Cập nhật gần nhất lúc: 2024-08-30 14:20:05