Synopsys - Design Verification Engineer (Mid-Senior)

Business Area Description
The Solutions Group high- quality, silicon- proven semiconductor IP solutions for SoC designs. The Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate IP integration, software development, and silicon bring- up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre- verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits. Synopsys&039; extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate time- to- market.
Introduction
Our Digital Team is seeking for great Design Verification engineer. Join with us if you are finding a job which challenge yourself with latest process technologies.
Opportunities

Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon.
Dedicated support from company for team building, social activities: Team trip, Family Day…
Competitive salary and benefit. Dedicated support from company for health: Insurance, Sport clubs: Football, Table- tennis, Badminton, Yoga, Zumba …
Chance to work with bleeding edge technologies that enable Data Center, AI/ML, 5G applications.
Professional, innovative, fair and fun working environment. Strong culture company.
SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented Viet Nam engineering team
Clear career path of self- development to either Technical Expert or Design Leader/Manager

Job Descriptions

Work in the RnD team to develop and validate for the high- bandwidth interface IP.
RTL, GLS & Co- simulations & coverage closure
Hands on experience in creating detailed Verification Environment from Functional Specifications
Writing test cases, checkers, and doing coverage report.
Debug of simulations, including those of real signals modeled using SV for analog.
Take part in technical reviews, peer review.
Follow and improve development process ensuring high quality output.

Great team player, willing to support others.
Excellent debug skills and demonstrated experiences in Perl /TCL/Python scripting is a plus.
Accountable, result oriented and good English communication.
Experience in skill with design tools: VCS, Verdi. Familiar Formal verification tool (vc_formal) is a plus.
2+ years of experience in Design Verification
BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
Self- motivated and enthusiasm in technology and problem solving.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Laptop, Chế độ bảo hiểm, Du Lịch, Phụ cấp, Chế độ thưởng, Chăm sóc sức khỏe, Đào tạo, Tăng lương, Nghỉ phép năm, CLB thể thao

Cập nhật gần nhất lúc: 2024-04-03 10:59:01