System Integration Senior Manager

● Integrate controller and PHY at RTL level
● Generate HDM model (subsystem CDC model, for SOC level CDC)
● Integrate controller and PHY IP level SDC and generate subsystem level SDC
● Pass SOC, subsystem simulation
● SOC Integration (IP Connectivity, IP Configuration, Bus Protocol Design etc)
● Subsystem Integration (PCIe, DDR, USB etc)
● Pass QA items such as LEC, STA, In- house Design Kit
● Generate subsystem document & database package
● Perform Synthesis (RTL to Netlist)
● Pass RTL QA items such as CDC, Lint, SDC validation
● Project Management and provide weekly progress update to Customers

● Experience in UVM is a plus
● Familiar with Front- end EDA tools- Logic simulation tool, Cadence Xcelium or Synopsys VCS- Synopsys Design Compiler, PrimeTime, Lint- LEC tool, Cadence Conformal or Synopsys Formality- Clock Domain Crossing (CDC) tool, Synopsys SpyGlass or Mentor Graphic Questa CDC
● Candidate with 8 years experience or more will be considered for technical lead position ● Candidate with lesser experience will be considered for junior position.
● Min 2 years working experience
● BS or MS degree in EE or CS related
● Good English communication skills
● Familiar with System Verilog
● Familiar with PCIe Gen- 4 spec
● Familiar with AMBA AXI, AHB, APB spec

- Intensive training on the job.
- Attractive salary, allowance and bonus with annual revision.
- People values, social responsibility, and sustainability.
- Opportunities for self- development and career advancement
- Strong team spirit in an entrepreneurial environment of a growing company.

Cập nhật gần nhất lúc: 2024-05-11 22:00:02