Design Verification Engineer

Enterprises across industries stand at an inflection point today. In order to thrive in the digital age, technologies such as analytics, cloud, IoT, and automation occupy center stage. In order to offer enterprises the maximum benefit of these technologies to further their business objectives, HCL offers an integrated portfolio of products and services through three business units. These are IT and Business Services (ITBS), Engineering and R&D Services (ERS), and Products and Platforms (P&P).

ABOUT USHCL Technologies is a next- generation global technology company that helps enterprises reimagine their businesses for the digital age. Our technology products and services are built on four decades of innovation, with a world- renowned management philosophy, a strong culture of invention and risk- taking, and a relentless focus on customer relationships. HCL also takes pride in its many diversity, social responsibility, sustainability, and education initiatives. Through its worldwide network of R&D facilities and co- innovation labs, global delivery capabilities, and over 187,000+ ‘Ideapreneurs’ across 50 countries, HCL delivers holistic services across industry verticals to leading enterprises, including 250 of the Fortune 500 and 650 of the Global 2000.

Position: Verification/ Logic Design Engineer (Hanoi & HCMC)
Location: Ha Noi, Ho Chi Minh

To be responsible for providing technical guidance or solutionsTo develop and guide the team members in enhancing their technical capabilities and increasing productivity
To be responsible for managing technology in projects and providing technical guidance or solutions for work completion
To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations.
To ensure process compliance in the assigned module, and participate in technical discussions or review.

REQUIREMENTS:

Good understanding of ASIC/SoC life cycle
Experience with Testbench development/modification , Test case development, coding, execution, bug analysis, Regressions, coverage analysis ,Verification closure
Experience with Gate level simulations
3+ years of Experience.
Experience in prevalent standards & Protocols viz. PCIe Gen3/4/5/USB3/DDR4/5, /Ethernet / CSI2 / I3C / AMBA
Experience in OVM/UVM methodologies using SV
Bachelors/Masters degree in Electronics /Electrical Engineering with 5+ year’s experience in verification
Should have participated in multiple ASIC/SoC verification till tape out stage
Experience with Full chip test plan development/modification
Experience in scripting

BENEFIT:

18 paid leaves per year (including 12 annual leaves + 6 personal leaves)
Working in a fast paced, flexible, and multinational working environment. Chance to travel onsite (in 49 countries).
Insurance plan based on full salary + 13th salary
Internal Training (Technical & Functional). Scope of English Training.
Medical Benefit for Employee and Family.
Working time: 8:30 AM- 6:00 PM From Mondays to Fridays.
100% full salary in probation period.

Cập nhật gần nhất lúc: 2025-08-12 23:55:02