Requirements
· Require having at least 3+ years’ experience on managing and leading teams in chip design industries.
· Individual who consistently look for ways to do things more efficiently while upholding quality. Passionate in solving problems, ability to synthesize data and translate into data driven proposals and decisions.
· Excellent analytical, problem solving and debugging skills with strong interest in semiconductor technology.
· Use of industry standard placement and routing CAD tools
· Proficient in full ASIC design cycle: requirements definition, architectural and micro- architectural specification, RTL, design verification, floor- planning, synthesis, timing closure, post- silicon validation.
· Fluency in scripting languages (TCL, PERC, Python) and ability to develop tools for ASIC automation.
· Have a Bachelor/ Master’s degree in relevant field (Electrical and Electronics or Computer System) with at least 8++ years of experience both in managing and leading a technical team (either on Chip design or CAD methodology domain).
· Experience in Block floor planning, RTL to gate level netlist generation through synthesis, DFT insertion, placement, clock tree synthesis and route flows, power and static timing analysis and closure, validation of physical design including timing, electrical rules, DRC/LVS, noise, RV checks, formal equivalence verification.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self- driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
