Synopsys - Senior DFT Engineer

Business Area Description
The Solutions Group high- quality, silicon- proven semiconductor IP solutions for SoC designs. The Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate IP integration, software development, and silicon bring- up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre- verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits. Synopsys&039; extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate time- to- market.
Introduction
Our Digital Team is seeking for DFT Senior engineer. If you are an experienced DFT engineer who wants to join a team of experts in IC design with the latest process technologies, this can be a perfect position for you.
Opportunities

Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon.
Professional, innovative, fair and fun working environment. Strong culture company.
Clear career path of self- development to either Technical Expert or Design Leader/Manager
Chance to work with bleeding edge technologies that enable Data Center, AI/ML, 5G applications.
Competitive salary and benefit. Dedicated support from company for health: Insurance, Sport clubs: Football, Table- tennis, Badminton, Yoga, Zumba …
Dedicated support from company for team building, social activities: Team trip, Family Day…
SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented Viet Nam engineering team

Job Descriptions

Analyze and improve test coverage
Make DFT integration guidelines to SoC level
Complete all design quality checks and data quality checks
Define and implement DFT architecture of IP design
STA DFT timing constraints develop and analysis
Do SCAN insertion and ATPG simulation (with and without timing)
Do FMEDA, DFMEA analysis and report.

Requirements:

BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
Strong knowledge of DFT architecture & methodologies which includes Scan insertion, ATPG, JTAG.
Design experience in MBIST, LBIST and Analog DFT is an added advantage
Highly responsible, result oriented
Solid skill with design tools: Synopsys Design Compiler, VCS, Formality, TetraMAX
Good English communication both verbally and in writing
Solid debug skills and demonstrated experiences in Perl/TCL/Python scripting is a plus
4+ years working experience in DFT design
Great team player, willing to support others

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Laptop, Chế độ bảo hiểm, Du Lịch, Phụ cấp, Chế độ thưởng, Chăm sóc sức khỏe, Đào tạo, Tăng lương, Nghỉ phép năm, CLB thể thao

Cập nhật gần nhất lúc: 2024-04-03 11:11:48